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Amd Apu Gray Hawk 2019 Navi Starship

Posted on May 27, 2022 by Marie A. Dean

AMD EPYC Server Processor Thread – EPYC 7000 series specs and performance leaked

Page 14 – Seeking answers? Bring together the AnandTech community: where nearly half-a-one thousand thousand members share solutions and talk over the latest tech.



Sep 18, 2000


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  • #326
And then Rome is Zen2 Epyc and should plug-in to current Epyc servers if I’grand reading correctly. Also as currently being worked on and beingness debugged.



October 19, 2000


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  • #327
Then Rome is Zen2 Epyc and should plug-in to current Epyc servers if I’m reading correctly. As well as currently being worked on and being debugged.

Drop in will exist up to the OEMs. But yep this platform should be skillful for three-5 years before any major updates.



Aug 23, 2012


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  • #328
Here nosotros take multiple sources confirming that GF 7LP is launching with a process for loftier performance .

http://www.anandtech.com/bear witness/11558/globalfoundries-details-7-nm-plans-three-generations-700-mm-hvm-in-2022

The seven nm platform of GlobalFoundries is called 7LP for a reason — the company is targeting primarily high-performance applications, not merely SoCs for smartphones, which contrasts to TSMC’s approach to 7 nm. GlobalFoundries intends to produce a diversity of chips using the tech, including CPUs for high-performance calculating, GPUs, mobile SoCs, chips for aerospace and defence, as well as automotive applications. That said, in addition to improved transistor density (upwardly to 17 million gates per mm2 for mainstream designs) and frequency potential, GlobalFoundries likewise expects to increase the maximum die size of 7LP chips to approximately 700 mm², up from the roughly 650 mm² limit for ICs the visitor is producing today. In fact, when it comes to the maximum die sizes of fries, there are certain tools-related limitations.

For their newest node, the company is focusing on 2 ways to reduce power consumption of the fries: implementing superior gate control, and reducing voltages. To that finish, chips made using GlobalFoundries’ 7LP technology volition support 0.65 – 1 V, which is lower than ICs produced using the company’s 14LPP fabrication process today. In addition, 7LP semiconductors will feature numerous work-functions for gate control.

https://world wide web.semiwiki.com/forum/content/6837-globalfoundries-7nm-euv-update.html


GF however is leading with a high operation (LP equals Lead Operation in IBM speak) version of 7nm for AMD while TSMC is first with a low power version of 7nm for Apple tree, Qualcomm, MediaTek, and the other SoC vendors.

https://world wide web.globalfoundries.com/sites/default/files/production-briefs/7lp-product-brief.pdf
http://semimd.com/chipworks/2017/01/xviii/iedm-2016-setting-the-stage-for-75-nm/


Four Vt options are available in the TSMC vii-nm technology [1] . There are iv device Vt options with a range of ~200 mV.

GF 7LP provides option of 5 cadre device Vt compared to TSMC which provides iv. Here again the requirement to back up very high performance 5 Ghz and low power mobile is driving the need to provide a broader range of Vt and higher Vt.

TSMC is launching offset with a low power mobile version of N7 for its primary client Apple and GF is launching with a high functioning version of 7LP for AMD. Its going to be interesting to see the comparison of products manufactured at TSMC N7 HPC for Nvidia vs GF 7LP for AMD in 2022.



Jul eighteen, 2010


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  • #329
Here nosotros have multiple sources confirming that GF 7LP is launching with a procedure for high performance .

http://www.anandtech.com/testify/11558/globalfoundries-details-seven-nm-plans-three-generations-700-mm-hvm-in-2022

The seven nm platform of GlobalFoundries is called 7LP for a reason — the company is targeting primarily high-functioning applications, not just SoCs for smartphones, which contrasts to TSMC’south arroyo to 7 nm. GlobalFoundries intends to produce a variety of chips using the tech, including CPUs for loftier-functioning computing, GPUs, mobile SoCs, fries for aerospace and defense, as well as automotive applications. That said, in addition to improved transistor density (upward to 17 million gates per mm2 for mainstream designs) and frequency potential, GlobalFoundries too expects to increase the maximum die size of 7LP chips to approximately 700 mm², up from the roughly 650 mm² limit for ICs the company is producing today. In fact, when it comes to the maximum die sizes of fries, there are sure tools-related limitations.

For their newest node, the company is focusing on two ways to reduce ability consumption of the chips: implementing superior gate command, and reducing voltages. To that end, chips fabricated using GlobalFoundries’ 7LP technology will support 0.65 – 1 5, which is lower than ICs produced using the company’s 14LPP fabrication process today. In improver, 7LP semiconductors will feature numerous work-functions for gate control.

https://www.semiwiki.com/forum/content/6837-globalfoundries-7nm-euv-update.html


GF however is leading with a high performance (LP equals Lead Performance in IBM speak) version of 7nm for AMD while TSMC is first with a low power version of 7nm for Apple, Qualcomm, MediaTek, and the other SoC vendors.

https://www.globalfoundries.com/sites/default/files/product-briefs/7lp-production-brief.pdf
http://semimd.com/chipworks/2017/01/18/iedm-2016-setting-the-stage-for-75-nm/


Iv Vt options are bachelor in the TSMC 7-nm technology [1] . In that location are four device Vt options with a range of ~200 mV.

GF 7LP provides choice of 5 core device Vt compared to TSMC which provides 4. Here once again the requirement to back up very high operation five Ghz and low power mobile is driving the need to provide a broader range of Vt and higher Vt.

TSMC is launching first with a low power mobile version of N7 for its primary client Apple and GF is launching with a high operation version of 7LP for AMD. Its going to exist interesting to see the comparison of products manufactured at TSMC N7 HPC for Nvidia vs GF 7LP for AMD in 2022.

Seeing that GloFlo is leading with a high power 7nm and TSMS with a low power one, what do see as the time divergence for TSMC to take the HPC version?



January 1, 2012


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  • #330
Seeing that GloFlo is leading with a loftier power 7nm and TSMS with a low ability 1, what practise see as the time difference for TSMC to accept the HPC version?

I’m not sure they would really. If your fabs are total and making money, so why would you modify horses so to speak? Comes down to money at the cease of the solar day. If your fabs are filled, why spend coin trying to fill up your fabs more…

moinmoin



Jun 1, 2017


three,308


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  • #331
TSMC is launching start with a low ability mobile version of N7 for its primary customer Apple and GF is launching with a high performance version of 7LP for AMD. Its going to be interesting to come across the comparing of products manufactured at TSMC N7 HPC for Nvidia vs GF 7LP for AMD in 2022.

Will be interesting how GloFo’southward and TSMC’s dissimilar approaches pan out.

In any case as mentioned before Lisa Su was quoted in the Q&A at the AMD Financial Analyst Twenty-four hours that AMD is working with both on 7nm, so AMD may well be able to pick TSMC if they require it for a more power efficient chip similar perchance in Ryzen Mobile (should be a skillful option to take if 7LP has areas where information technology’due south less efficient than the current 14LPP).
https://www.techpowerup.com/233389/amd-to-keep-working-with-tsmc-globalfoundries-on-vii-nm-ryzen

T1beriu


  • #332
Or AMD could be using TSMC for time to come panel SoCs or Navi.

Subsequently edit: I don’t think AMD has the resources to build Zen2 on two silicon architectures. I too don’t recall GF has the capacity to sustain IBM and AMD’s Ryzen and Radeon ramp upward on 7nm.

Last edited:
Jun 25, 2017

Ajay



Jan 8, 2001


eleven,218


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  • #333
Or AMD could be using TSMC for future console SoCs or Navi.

Afterward edit: I don’t retrieve AMD has the resources to build Zen2 on 2 silicon architectures. I besides don’t call up GF has the capacity to sustain IBM and AMD’due south Ryzen and Radeon ramp up on 7nm.

Yeah, if 7FF LP is GloFo only, every bit it appears, (no Samsung) then Zen2 won’t be going anywhere – peculiarly non to TMSC. On the plus side, Fab 28 is undergoing a 20% expansion. Fifty-fifty though some of u.s. wait Zen2 to use 6 core CCXs, that would still mean ~33% more than dice per wafer.

moinmoin



Jun ane, 2017


iii,308


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  • #334
Or AMD could be using TSMC for future console SoCs or Navi.

As we already have mid-gen refreshes for both consoles and Sony has stated they’ll nonetheless practice fully new gens a future console SoC may well be Zen based. And AMD did well in the past having evolution in the semi custom business feed dorsum into their main business organisation.



Jun 23, 2012


1,522


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  • #336
Here we take multiple sources confirming that GF 7LP is launching with a procedure for high performance .

http://www.anandtech.com/show/11558/globalfoundries-details-7-nm-plans-3-generations-700-mm-hvm-in-2022

The 7 nm platform of GlobalFoundries is called 7LP for a reason — the visitor is targeting primarily high-functioning applications, not just SoCs for smartphones, which contrasts to TSMC’southward approach to 7 nm. GlobalFoundries intends to produce a variety of chips using the tech, including CPUs for high-functioning computing, GPUs, mobile SoCs, fries for aerospace and defense force, as well as automotive applications. That said, in addition to improved transistor density (up to 17 1000000 gates per mm2 for mainstream designs) and frequency potential, GlobalFoundries also expects to increase the maximum dice size of 7LP chips to approximately 700 mm², up from the roughly 650 mm² limit for ICs the company is producing today. In fact, when it comes to the maximum die sizes of chips, there are certain tools-related limitations.

For their newest node, the company is focusing on two ways to reduce power consumption of the chips: implementing superior gate control, and reducing voltages. To that end, chips fabricated using GlobalFoundries’ 7LP technology will back up 0.65 – ane 5, which is lower than ICs produced using the company’s 14LPP fabrication process today. In improver, 7LP semiconductors will feature numerous work-functions for gate control.

https://www.semiwiki.com/forum/content/6837-globalfoundries-7nm-euv-update.html


GF yet is leading with a high performance (LP equals Lead Operation in IBM speak) version of 7nm for AMD while TSMC is first with a low power version of 7nm for Apple, Qualcomm, MediaTek, and the other SoC vendors.

https://www.globalfoundries.com/sites/default/files/product-briefs/7lp-product-brief.pdf
http://semimd.com/chipworks/2017/01/18/iedm-2016-setting-the-stage-for-75-nm/


4 Vt options are available in the TSMC seven-nm engineering [ane] . There are four device Vt options with a range of ~200 mV.

GF 7LP provides choice of 5 core device Vt compared to TSMC which provides 4. Hither over again the requirement to back up very loftier performance v Ghz and low power mobile is driving the need to provide a broader range of Vt and higher Vt.

TSMC is launching kickoff with a low ability mobile version of N7 for its primary customer Apple and GF is launching with a high functioning version of 7LP for AMD. Its going to be interesting to run into the comparison of products manufactured at TSMC N7 HPC for Nvidia vs GF 7LP for AMD in 2022.

So basically,this might exist like the Phenom vs the Phenom II regarding a leap in clockspeeds?? I assume Ryzen MK3 will exist on 7NM,meaning some other two generations of IPC improvements,two years of better optimisations and higher clockspeeds – and so the all-time is even so to come it looks like.

NTMBK



November 14, 2011


9,698


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  • #337
Yeah, if 7FF LP is GloFo only, every bit it appears, (no Samsung) then Zen2 won’t be going anywhere – especially not to TMSC. On the plus side, Fab 28 is undergoing a 20% expansion. Even though some of us expect Zen2 to apply 6 core CCXs, that would withal hateful ~33% more dice per wafer.

Not sure that a 6 core CCX makes that much sense- you’re boosting the intra-CCX latency. My personal judge would be that they become to 3×4 per die, rather than 2×6.



Jun two, 2009


five,005


ane,336


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  • #338
Not certain that a six core CCX makes that much sense- you’re boosting the intra-CCX latency. My personal guess would be that they go to 3×4 per dice, rather than 2×6.

But how exercise you make a dice of 3 ccx? would accept to exist a very “long” die but nor sure that is a problem simply maybe could be due to package size.

Atari2600



November 22, 2016


1,320


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  • #339
But how do you lot make a die of 3 ccx? would have to be a very “long” die but nor sure that is a problem but peradventure could be due to packet size.

For what purposes?

A 12 core is much more likely to exist a salvaged 16 cadre (4 ccx).

If information technology were an APU, and so you’d be looking at either a 4 cadre (i ccx) or 8 core (2 ccx) along with iGPU.

A 24 cadre would salvaged from the full fat 48 core 12 ccx.

A 48 cadre would be 12 ccx (6 zeppelin equivalent). [Meet image below for logic. 48Core Starship and peradventure more relevantly, 4core Grey Hawk]

NTMBK



Nov 14, 2011


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  • #340
Simply how do you lot brand a die of 3 ccx? would have to be a very “long” die merely nor sure that is a problem merely maybe could be due to package size.

Hmm, proficient point. Mayhap they could change the internal layout of a CCX, and then that instead of a 2×2 tile it’southward a 1×4? *not a processor engineer*



Jul eighteen, 2010


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  • #341
Hmm, good bespeak. Mayhap they could modify the internal layout of a CCX, and then that instead of a 2×2 tile information technology’s a 1×4? *not a processor engineer*

I remember the new AMD is going to make as few key changes as possible for the needed performance. Nosotros are seeing their philosophy as getting the most out of as fiddling every bit possible starting to payback in a big way. Don’t expect that to modify for the next few years at least.

  • #342
Non sure that a 6 core CCX makes that much sense- you’re boosting the intra-CCX latency. My personal guess would be that they get to 3×4 per die, rather than 2×6.

Do you mean latency within one CCX? Isn’t the bigger issue the latency between CCX? If then information technology would seem that more cores per complex increases the chances of not needing to get exterior to get data, and conversely that more than CCX = more than big-latency hits.



Mar 10, 2017


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  • #343
I’m not sure that a vi cadre ccx makes much sense from a layout betoken of view. I would imagine that it has other internal addresting issues to argue with. Instead, I would imagine that with their current packaging dimensions, you lot could see a switch to 4 CCXS per bit. Or, as an alternative, proceed with ii CCXs, only add an “L4 cache” that is on the order of 256MB or larger.

Bold that they stay with similar dimensions to the current dies, and that the physical interface sections of the dies can’t compress much more to maintain the ability to link to the substrate traces, the CCXS volition accept to modify layout to fit if they are larger than 6 cores and keep a double row organisation. If they rotate the ccx units 90 degrees, then they can fit ii rows of 4 with a common L3 between the rows. That’s going to allow the L3 to double, but will likely add a bit of latency for DRAM controller admission due to a longer routing trace in the chip. All of that is contingent on there being no major changes to the relative core dimensions with the compress and revision.

Once again, I’thousand no proficient and this is just my opinion.

Terminal edited:
Jun 26, 2017

Ajay



Jan 8, 2001


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  • #344
Not sure that a 6 cadre CCX makes that much sense- you’re boosting the intra-CCX latency. My personal gauge would be that they go to 3×4 per dice, rather than 2×6.

How much would the latency increase, specially on GF’s 7FF? I don’t know either, but I’m certain it would be worth it rather than having more inter-CCX latency. It’s a matter of design and AMD has known for a while what they want @ 7nm. Nosotros will see if AMD had the $$s to redesign the CCX after two iterations. If they did redesign information technology, they tin can go with an APU with up to six cores using just i CCX.

Edit: didn’t see that roadmap posted by Atari2600. Then the respond is that AMD is sticking with a 4 core CCX. It certainly makes sense financially.

Edit2: Dang slide is from a clickbait site
o_O

Last edited:
Jun 26, 2017

T1beriu


  • #345
Edit2: Dang slide is from a clickbait site

I would freak out as well, but the original source for the slide is the opposite of a clickbait site.

  • #346
If they build supermicro 1s boards I might consider ownership EPYC. Seems Intel is leaving out 1s support with the Purley platform…. Not really happy virtually that…



Oct 19, 2000


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Jan 1, 2012


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  • #348
If they build supermicro 1s boards I might consider buying EPYC. Seems Intel is leaving out 1s back up with the Purley platform…. Not really happy about that…

You will find them here. Supermicro Epyc Servers and Motherboards

Markfw

Markfw

CPU Moderator, VC&G Moderator, Elite Member



May sixteen, 2002


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  • #349
Wow. I just figured this out…. The most I can find for DDR4 ECC registered is 64 gig modules. That motherboard I saw (H11DSi) has 16 slots and supports up to 2 TB memory 2666. And then for 1 TB (64*sixteen) DDR4 2133 (fastest I could find) and 2 32 core, 64 thread CPU’s, and just guessing on $1000 motherboard with HSF’s that 25k for 128 threads, and one TB memory, simply WOW, not bad (for enterprise form hardware)

The retention was $1849 for 2 64 gig retention sticks = ~15k + mobo+ 8k for 2 processors.

thecoolnessrune



Jun 8, 2005


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  • #350
Wow. I just figured this out…. The most I tin can find for DDR4 ECC registered is 64 gig modules. That motherboard I saw (H11DSi) has sixteen slots and supports upwardly to ii TB memory 2666. So for 1 TB (64*16) DDR4 2133 (fastest I could detect) and 2 32 cadre, 64 thread CPU’s, and merely guessing on $1000 motherboard with HSF’s that 25k for 128 threads, and 1 TB memory, just WOW, great (for enterprise grade hardware)

The memory was $1849 for ii 64 gig retention sticks = ~15k + mobo+ 8k for ii processors.

I know through my workplace that HP has validated DDR4 2400 128GB 8x rank DIMMs. You’ll pay a premium for them though.
:)
https://www.cdw.com/store/products/HPE-DDR4-128-GB-LRDIMM-288-pin/4286681.aspx#PO

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Amd Apu Gray Hawk 2019 Navi Starship

Source: https://forums.anandtech.com/threads/amd-epyc-server-processor-thread-epyc-7000-series-specs-and-performance-leaked.2508848/page-14

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